Bertech showcased advanced packaging applications at SEMICON Taiwan 2026. Photo provided by PARAGON

Economic Daily News Reporter Hsu Mu-Chun/Instant Report

PARAGON (3518) and its subsidiary Crystal Materials will jointly participate in SEMICON Taiwan 2026, the international semiconductor exhibition. Leveraging years of experience in vacuum vapor deposition (PVD) technology and material processing capabilities, Bertech continues to focus on high-power devices and advanced packaging applications. This time, they will showcase their key “titanium/copper seed layer” coating technology, with highlights covering silicon carbide (SiC) wafers, HDI substrates, ABF substrates, aluminum nitride (AlN) ceramic substrates, through-glass vias (TGV), silicon carbide through-hole vias (TSiCV), SiC microchannels, and other applications.

Titanium-Copper Seed Layer: A Key to Advanced Packaging Metallization

In the metallization process of advanced packaging and advanced substrates, the uniformity, continuity, and interfacial adhesion of the seed layer are crucial factors affecting the quality of subsequent copper plating and packaging reliability. Through optimized PVD process technology, Bertech can form titanium adhesive layers and copper conductive seed layers with excellent uniformity and adhesion on various substrates, thereby improving the interfacial quality between the metal layer and the substrate and meeting the stringent requirements of high-density interconnect structures for metallization processes.

Compared to some traditional wet metallization processes, PVD offers advantages such as dry processing and high film purity. Addressing the challenges of microvias and high aspect ratio structures, Bertech continues to optimize process parameters and plasma technology to improve the coverage, continuity, and adhesion of the seed layer. This advantage has been successfully extended to high-end materials such as ABF substrates and AlN ceramic substrates, further meeting the technological demands of ultra-fine line manufacturing.

Laying the Foundation for Next-Generation Packaging: From TGV to TSiCV

Beyond advanced substrate applications, PTTECH Technology is also actively showcasing its emerging and forward-looking applications to meet the demands of next-generation AI chip packaging for panel-level packaging and efficient heat dissipation. Glass substrates, due to their high flatness, dimensional stability, and excellent high-frequency electrical characteristics, are considered a highly promising next-generation substrate material for advanced packaging. PTTECH Technology has developed titanium-copper seed layer technology to address the adhesion between glass and metal and the metallization requirements of deep-hole structures. This technology continuously optimizes the film coverage and uniformity in microporous structures, laying the foundation for subsequent copper plating and redistribution layer (RDL) processes on glass substrates.

Simultaneously, for high-power SiC device applications, PTTECH Technology is also developing TSiCV and wafer back-side metallization (BGBM) processes. Through surface pretreatment and titanium-copper metallization technology, it improves the interface quality between the SiC substrate and the metal layer, thereby meeting the requirements of high-power devices for low-resistance metallization, high reliability, and packaging integration.

Substrate circuitry application. Photo provided by PTTECH Technology

Breaking through the high heat flux challenge: Wafer-level SiC microchannel cooling technology

Faced with the high heat flux challenges brought by high computing power and AI data centers, traditional air cooling and external liquid cooling solutions have limited heat dissipation capabilities for localized hot spots. Berton Technology combines the high thermal conductivity of SiC with precision processing technology to provide a “wafer-level microchannel” direct cooling solution. By integrating microchannels into the SiC substrate close to the heat source, the high thermal conductivity and excellent thermal stability of SiC materials can be leveraged to quickly eliminate temperature differences at hot spots, providing an ultimate solution for high-pressure microchannel heat dissipation.

Furthermore, the coefficient of thermal expansion of SiC is similar to that of silicon wafers, which helps reduce interfacial thermal stress, thereby reducing the risk of package structure warpage and interface delamination. With these characteristics, SiC microchannels are expected to meet the structural reliability requirements under coolant circulation and long-term operation, significantly improving the long-term reliability of advanced packaged devices.

SiC wafer regeneration and thinning applications. Photo provided by PTTECH Technology

PVD seed layer technology combined with SiC materials expands the supply chain footprint

PTTECH Technology, founded on its early EMI/ESD vacuum sputtering applications in 3C products, has actively invested in advanced process technology development in recent years. It possesses silicon carbide material supply, silicon carbide precision machining technology, and vacuum coating physical vapor deposition technology, providing comprehensive vertically integrated services from “front-end R&D and design” to “back-end mass production.” Simultaneously, through its subsidiary, Crystal Materials, it is developing and manufacturing SiC wafers, assembling a top-tier compound crystal expert team to create a high-specification, high-yield, vertically integrated one-stop production system.

The titanium-copper seed layer technology to be showcased at SEMICON Taiwan 2026 not only reflects PTTECH’s technological extension in dry coating processes but also demonstrates the company’s continued technological strength and strategic layout in penetrating the high-power device, advanced packaging, and third-generation semiconductor markets.

SEMICON Taiwan is one of the best business matching platforms for plenty of companies, aiming to not only advance technological frontiers, but also bring innovation in various kinds of technologies forward. For semiconductor players who are closely connected with the global supply chain, SEMICON Taiwan is also an excellent opportunity to showcase the latest solutions, whereas it is a must-visit for visitors to get to know what’s new from thousands of exhibitors in a short time.

參展櫃位I3323

Glass-Interposer technology brings 2D-to-3D advanced packaging with more stable yields and more competitive cost. As semiconductor processes continue to advance, the aspect ratio of vias linking layers keeps increasing. ITRI’s “High Aspect-Ratio Glass-Substrate Via-Fill Electroplating and Inspection Technology” effectively raises electrode density and improves chip stacking, helping Taiwan’s semiconductor industry stay ahead—earning ITRI’s Outstanding Research Gold Award.

With the 5G era and the rise of AI, IoT, and connected vehicles, semiconductors continue to scale to 7 and 5 nm—and toward 3 and 2 nm—nearing Moore’s-Law limits, driving the need for new routes. Heterogeneous integration, which stacks different electronic components into a single chip via 2.5D or 3D design, has emerged as a key breakthrough.

Leading technology—world’s highest aspect ratio

Traditional 2D packaging mounts chips side-by-side on a single plane. As chips trend toward thinner, lighter, smaller—while requiring more compute and lower power—2D packaging can no longer meet industry demand. 3D packaging breaks the horizontal constraint by vertically stacking different-function chips via heterogeneous integration, dramatically boosting module compute capability.

Interposer technology is one key to heterogeneous integration. Glass interposers offer low warpage, faster signal transmission, and better power efficiency—and they meet thin-and-light requirements, making them an increasingly favored option. Interposers require metal interconnects between layers, so vias are drilled in the glass. As processes advance, the via aspect ratio (AR) continues to grow.

“Aspect ratio” (also called depth-to-width ratio) is the ratio of via depth to diameter. Huang Meng-Chi, deputy general director of ITRI’s Mechanical and Mechatronics Systems Research Laboratories (Advanced Mechanical Technology Division), explains: with more 3D stacking layers, vias must go deeper; as chip sizes and line/space shrink, via diameters shrink too. Small-diameter, high-AR vias are therefore an inevitable trend—but the higher the AR, the harder the process, a key challenge for the industry.

“It’s like constructing a high-rise: floors are stacked, and the glass substrate is the floor between levels. You must drill through to connect circuits and pipes between floors so utilities flow normally,” Huang explained.

Over five years, ITRI led the world in developing this technology. Through-Glass Vias (TGVs) connect upper and lower metal traces, transmitting power and signals to optimize chip performance. “ITRI’s technology ensures signal and power quality even as ‘the building’ gets taller,” Huang said.

Wet metal-plating deposition—achieving the highest AR

Many international teams research high AR, but most reach only AR 10—far short of ITRI’s solution. ITRI’s lead rests on three key technologies. First, a brand-new via-fill electroplating process: a glass through-via substrate serves as the interposer, with copper plated to fill the vias and connect upper and lower circuits. To improve metal-glass adhesion, a 100–200 nm composite oxide conductive thin film is formed on the glass surface before filling, acting as a bonding bridge.

Industry typically forms this film via dry-plus-wet processes—using PVD vacuum plasma deposition to drive metal ions into the via. But more stacked layers means deeper vias, making precise filling harder and lowering yield. ITRI developed a low-cost composite oxide conductive thin film suitable for high AR using an all-wet process: by immersing in inorganic-oxide and electroless-copper solutions that flow through the deep vias, an oxide film forms on the surface; a low-temperature co-firing step creates intermetallic compounds between the metal-oxide film and the glass, overcoming the poor glass-metal adhesion barrier.

“With traditional processes, AR 15 is the limit,” Huang said. The all-wet process achieves AR 15–30, with seed-layer deposition rates above 70% and good coverage. Given the high cost of PVD tools, switching from dry-plus-wet to all-wet equipment can save about 50% in cost—meaningful relief for manufacturers.

Single-agent, dual-function plating additive—seamless fill

The second highlight is the development of a single-agent, dual-function via-fill plating additive. Normally, when filling vias with copper, plating is fastest at the surface and slowest at the center, causing voids; under high currents these voids cause rapid chip failures. Special additives are therefore used to slow plating at the via mouth so the center fills first, before the mouth closes—reducing voids.

To solve this, industry commonly uses three additives at once; but each is consumed at a different rate and must be replenished, and they interfere with one another—making it hard to know what or how much to add. The team chose to develop a new additive from scratch: “starting with literature surveys to identify chemicals that might meet the functional needs, then screening one by one,” Huang said.

After exploration, the team identified several candidates and ran formulation experiments. Lead developer Chang Yu-Hsiang (ITRI Mechanical & Mechatronics) spent six months almost daily in the lab, meticulously recording each step, and carefully chose a chemical never before used in electroplating—surprisingly possessing both suppression and leveling functions, with excellent results even on its own. “As a single-agent via-fill plating, it not only solves coverage issues but also reduces measurement interference from multiple additives, improving process stability and yield. Compared with current industry formulations, it can save 50% in cost,” Huang said excitedly.

Schematic of chip heterogeneous integration—fan-out panel-level packaging as an example.

3D micro-void inspection—nowhere for defects to hide

The third highlight is an advanced 3D Sphere-Fitting algorithm for inspecting high-AR copper via fills. Huang noted that this was the most challenging and difficult part of the development. Structures and chemistries can be tuned by the team, but only direct inspection reveals whether vias are properly filled from edge to center, or where voids hide—visible to neither the naked eye nor conventional microscopes. “Skipping inspection is like developing blindfolded—you can’t improve.”

Initially the team outsourced inspections; each substrate took half a day, and 3D X-rays required manual checks; iterating on multiple formulations could take 1–2 weeks. Fortunately, in-house materials experts pitched in to develop an enhanced 3D sphere-fitting algorithm. Using high-resolution, high-contrast nano-tomography, software analyzes micro-void distributions and diameters within the structure to find defects quickly and accurately. “Its biggest breakthrough is the ability to inspect hundreds of TGV copper fills simultaneously, returning results in 1–2 days—greatly reducing inspection and correction time,” Huang said.

Dr. Lin Tzu-Hung, ITRI Materials and Chemical Research Laboratories, noted that similar void-detection techniques are used in biomedical materials and oil exploration—e.g., dental dentin microtubules and petroleum reservoir analysis. Applying automated void detection with nano-CT 3D inspection in the electronics industry is a first, and a new attempt for materials. “The challenge is that copper scatters X-rays, so software must remove noise and scatter to build a clear 3D axis. Once defined, the program quickly and automatically identifies the position, axial orientation, and locations of voids and defects within the metal columns. With precise coordinates, electron microscopes can then confirm at higher resolution, guiding corrections,” Lin said.

Through accurate inspection, the team felt their progress. “In early days, technology was less refined—voids were huge, like cracks down the middle of a baseball bat. As we refined the process, voids shrank to peanut-sized holes 2–4 μm across; today we can’t even find any voids,” Huang said with a satisfied smile.

Strategic preparation for the semiconductor industry—generating NT$100B+ value

This technology applies to fan-out panel-level packaging (FOPLP), HDI PCBs, and IC substrates, meeting the needs of advanced electronics processes. Huang noted that although the technology covers only part of the packaging process, key developments such as wet equipment and the single-agent additive shorten cycle time and save manufacturers at least 30% in equipment and chemical costs—estimated to create hundreds of billions of NT$ in value.

Another significance is enabling cross-industry collaboration: a globally known glass supplier traditionally focused on displays expanded into semiconductors through this project, gaining a new product direction; meanwhile, two Taiwanese equipment makers partnering with ITRI on chemicals and tools entered advanced semiconductor packaging equipment for the first time, building next-gen domestic equipment capability.

Huang revealed that current industry production requirements call for AR ~7–8, expected to rise to 10–15 in 2–3 years—ITRI is preparing the industry ahead of time. Pilot testing is under way at major OSAT facilities, and the team continues to refine the technology, hoping for early mass production to land innovation in Taiwan and maintain the semiconductor industry’s leading edge.

Cross-section SEM of high-AR plated via fill: 10 µm opening, ~120 µm depth, 3.5–5.3 µm surface copper, AR ~12—surpassing industry levels.

Source:
ITRI, Industrial Technology and Information Monthly.

Horizontal interconnect: Redistribution Layer

With growing AI compute demand and surging die-to-die data traffic, horizontal signal interconnects between dies are increasingly important. The key structure of advanced packaging is the horizontal interconnect, where RDLs play a core role in high-density signal routing and heterogeneous integration. An RDL is mainly composed of metal conductors, insulating dielectrics, and protective coatings. Depending on the substrate, an RDL can form either an RDL Interposer or a Silicon Interposer. Table 1 compares the two.

Table 1. Comparison of RDL Interposer and Silicon Interposer

1. RDL Interposer

The RDL Interposer replaces the conventional silicon substrate with a stack of multiple RDL layers, supporting the wiring structure with an organic dielectric rather than silicon. This approach achieves interconnect density approaching that of a silicon interposer, supports multi-chip integration, and lowers cost. The dielectric in this structure emphasizes lithographic performance and process efficiency; photosensitive polyimide (PSPI) is used because it can be exposed and developed directly after coating, eliminating extra photoresist and etch steps, shortening the process flow, and improving line resolution.

2. Silicon Interposer

A silicon interposer is built on a silicon wafer with fabricated TSVs and RDLs, providing high-speed chip-to-chip interconnect over a localized area. Unlike the organic dielectric of conventional RDLs, silicon-interposer RDLs use an inorganic dielectric—most commonly SiO2—offering low leakage, high reliability, and good thermal stability.

Vertical interconnect

2. Through-Silicon Via (TSV)

TSVs appear primarily in two contexts: TSVs in 3D packaging and TSVs in 2.5D interposers. Although both are silicon-via technologies, they differ markedly in purpose, dimensions, density, and applications. 3D TSVs are mainly used to vertically stack multiple dies—for example, memory stacks or direct stacking of logic and memory. They are typically smaller and higher-density, carrying vertical signals and power between layers, and emphasize short-distance, high-speed transmission with low latency. TSVs on a silicon interposer route signals vertically from a die into the interposer, where the RDL then distributes them horizontally to other dies or external interconnects. Interposer TSVs are relatively larger and lower-density; this structure falls within the 2.5D packaging category. Table 2 compares TSVs used in 2.5D vs. 3D applications.

Table 2. Comparison of TSVs in 2.5D and 3D applications

★This article is excerpted from Industrial Materials Magazine, Issue 466. Please refer to the attachment for full content.

Suitability of wide-bandgap materials by voltage requirement

Silicon-based power devices and modules have hit a wall in high-power demand; wide bandgap is a defining feature of compound semiconductors, so researchers turn to compound semiconductors for suitable materials and technologies. GaN transistors are suited to power devices in applications below 600 V; between 600–1,200 V, SiC transistors or modules increasingly take over—a range that today is also the GaN market. With careful circuit design, GaN modules can reach 900 V, so the 600–900 V market remains a competitive arena where products from different vendors can coexist; near 1,200 V and especially 1,700 V and above, SiC transistors dominate.

GaN-on-SiC is used for high-frequency HEMTs (High Electron Mobility Transistors); SiC-on-SiC is used for power semiconductors such as SBDs and FETs. SiC-on-SiC is growing rapidly as SBDs and FETs see growing use in power supplies. After 2025, broader HEV adoption is expected to drive even higher growth. SiC power devices are mainstream at 600–900 V, while 1,200 V SiC crystals are poised for rapid growth driven by 800 V battery vehicles, solar PV systems, and EV fast chargers.

Power devices on SiC substrates are mainly 6-inch wafers, which became mainstream from 2017. Competing silicon-based devices, MOSFETs and IGBTs, are mainly 8-inch wafers. SiC-SBDs are driving the SiC power-device market, with applications centered on communications equipment (server power supplies), EV charging stations, and on-board chargers in the automotive sector—markets that continue to expand.

Common materials in power-device and module packaging

In semiconductor packaging, packaging a single chip is called a “device”; packaging two or more chips with internal wiring is called “module packaging.” For device packaging, the chip is typically attached to the leadframe’s central pad with die-attach adhesive, with wire bonding connecting pads to leadframe pins; molding compound then encapsulates and protects the assembly (Fig. 4(a)). Because the circuit is simple, thermal management is handled mostly through the leadframe pins.

Fig. 4. (a) Power device; (b) module-packaging structure.

For module packaging—especially higher-power modules—thermal management is more critical. A common failure mode in power modules is thermally-induced cycling: mismatched coefficients of thermal expansion (CTE) cause delamination between the substrate and bonding-material layers, while gel fillers and resins inside the module that cannot withstand high temperature can fail. As shown in Fig. 4(b), in addition to wire interconnects between two chips, the chips are die-attached to a DBC (Direct Bonded Copper) substrate; the DBC is bonded to a baseplate; and thermal grease serves as the thermal interface material to the outer heatsink, creating a thermally-managed packaged module.

Silicon-carbide (SiC) industry structure

With its wide bandgap, high power density, high breakdown voltage, and good thermal conductivity, SiC is the material of choice for power devices and high-frequency substrates. Figure 7 shows the SiC industry structure, including single-crystal devices and power modules. Because SiC is used both as the main die in power modules and as an epitaxial substrate for high-frequency communications, the industry structure is divided into power semiconductors and RF semiconductors.

Fig. 7. Global industry structure of SiC wafers.

Leading global producers of SiC wafers for high power and high frequency include Cree and II-VI; SiCrystal is known for high-power applications. In Taiwan, GlobalWafers, WIN Semiconductors, Tankeblue (Sheng Hsin), and Hermes are active. Cree’s (now Wolfspeed) wafer sales are split between external and captive use; on the external side, Cree holds about 70% market share. ST-Micro has a long-term SiC wafer supply plan (US$220 million) and signed US$85 million 6-inch wafer supply agreements with ON Semiconductor and Infineon.

IEKView

Compound-semiconductor SiC is a key material for emerging industries spanning high frequency (5G/B5G/6G), satellite communications, IoT (smart cities), high power, and EV/xEV motors and green energy. Yet developing SiC still faces many difficulties—including downstream applications. The above is a partial excerpt; please refer to the attachment for full content.

★This article is excerpted from Industrial Materials Magazine, Issue 435. Please refer to the attachment for further details.

Silicon carbide (SiC) is best known as a wide-bandgap (WBG) material that powers highly efficient power electronics and accelerates the global green-energy transition. Yet its potential reaches far beyond power devices. As AI computing and 3D chip architectures push thermal-management demand sharply higher, SiC—with its outstanding thermal and mechanical properties—is opening a new wave of innovation in advanced packaging.

Why 12-inch SiC?

As AI accelerators and 2.5D/3D chip-stack densities continue to climb, heat dissipation has become the dominant limiter of system performance. TSMC, the world’s leading foundry, is actively developing 12-inch single-crystal SiC substrates whose thermal conductivity can reach about 500 W·m⁻¹·K⁻¹—far exceeding traditional ceramic materials such as alumina (Al2O3) and sapphire.

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The initiative, undertaken by TSMC together with partners and equipment suppliers, aims to replace existing ceramic substrates with SiC across a wide range of applications—from augmented-reality (AR) smart lenses to hyperscale data-center processors. In wearable AR lenses, for example, densely packed electronics must operate in tightly enclosed micro-spaces, where thermal control directly affects user safety and device reliability.

TSMC’s decision to exit gallium-nitride (GaN) and focus on new SiC applications reflects both competitive pressure and a rebalancing of its materials strategy. Leveraging SiC’s outstanding thermo-mechanical properties, TSMC is building a scalable, next-generation packaging platform.

Defect-density challenge for 12-inch SiC thermal substrates

While 12-inch SiC substrates for thermal management don’t require the ultra-low defect densities of power devices (MOSFETs, diodes, etc.), crystal integrity remains key to quality.

Structural defects such as micropipes, voids, and dislocations disrupt heat-flow paths, weaken mechanical strength, and impair surface flatness during grinding and CMP. As wafer diameter grows, warpage and deformation become more pronounced, directly affecting die-bond quality and advanced-packaging yield.

Because thermal transport in SiC relies on quantized lattice vibrations, any crystal defect that scatters or impedes phonons—micropipes, voids, dislocations—reduces thermal conductivity and creates local hotspots. The development emphasis therefore shifts from “eliminating electrically active defects” to “ensuring uniform bulk density, very low porosity, and excellent surface flatness”—the keys to high-yield, stable mass production of SiC thermal substrates.

Leveraging SiC’s thermal advantages

SiC combines high thermal conductivity, robust mechanical structure, excellent thermal-stress resistance, and chemical stability, making it ideal for handling the high heat fluxes in 2.5D and 3D chip designs.

In 2.5D integration, dies sit side-by-side on a silicon or organic interposer for short, fast, and power-efficient signal links. In 3D integration, dies are stacked vertically with very high interconnect density via TSVs or hybrid bonding.

Beyond passive cooling, SiC can also enable hybrid cooling schemes—pairing conventional substrates with high-conductivity materials such as diamond or liquid metals—to dramatically improve overall thermal management.

Materials-strategy pivot: from GaN to a renewed focus on SiC

TSMC plans to fully exit the GaN market by 2027 and refocus resources on SiC. Scaling to 12-inch wafers can bring cost benefits and improve process uniformity (fewer process-induced defects per unit area). Even so, crystal defect density, slicing, planarization, and wafer flatness remain core challenges for SiC manufacturing.

For a long time, SiC was virtually synonymous with power devices; now it is crossing into a new field where thermal management is the key bottleneck. TSMC is actively evaluating:

．Conductive N-type SiC as a high-thermal-conductivity substrate;

．Semi-insulating SiC as a potential interposer in chiplet-based architectures.

These directions could reshape the thermal-design architecture of AI accelerators and data-center chips, laying new foundations for future computing platforms.

Thermal management as a competitive edge: SiC breaks packaging thermal limits

In advanced semiconductor design, effective heat dissipation has become a critical differentiator. High-purity diamond reaches ~1,000–2,200 W·m⁻¹·K⁻¹, and single-layer graphene can hit 3,000–5,000 W·m⁻¹·K⁻¹—but both are costly, process-complex, and hard to scale.

Other alternatives—liquid metals, conductive adhesives, and microfluidic cooling—are promising but face cost, manufacturability, and integration trade-offs.

By contrast, SiC offers a pragmatic, balanced solution: strong thermal performance, robust mechanical strength, and scalable high-volume manufacturing—an ideal blend of performance and cost.

TSMC’s technological advantages and global positioning

TSMC’s deep experience in 12-inch wafer manufacturing, combined with its solid production base, rigorous process control, and packaging expertise, allows it to fold SiC into an end-to-end platform strategy—not merely a materials upgrade. This lets TSMC rapidly commercialize AI and HPC chips without restructuring its manufacturing system, cementing its lead in the global semiconductor supply chain.

TSMC’s SiC roadmap is evolving in parallel with paths like Intel’s Backside Power Delivery (BPD) and thermal-power co-design—signaling an industry shift in which thermal management is no longer a supporting function but a core of semiconductor innovation.

TSMC is not just improving heat dissipation; it is building a differentiated packaging platform for AI and HPC, making SiC a cornerstone of the future chip-packaging ecosystem.

Source:TSMC’s SiC Substrate Strategy: Scaling Thermal Performance for AI and 3D Packaging, by Filippo Di Giovanni; translated by Susan Hong.

Also published in EE Times Asia, November–December 2025 issue.

Company: Paragon (3518)

Subject: Plant renovation project carried out on behalf of subsidiary JingCheng Materials Co., Ltd.

Spokesperson: Liu Ming-Yi

Description:

1. Name and nature of the subject matter (e.g., land located at XX Section, XX Sub-section, North District, Taichung City):

Plant works and equipment.

2. Date of occurrence: 2024/12/26 – 2024/12/26.

3. Transaction unit quantity (e.g., XX square meters, equivalent to XX ping), unit price, and total transaction amount:

Unit quantity: Plant engineering and interior fit-out for the new plant.

Total transaction amount: estimated to be within NT$444.52 million.

4. Counterparty and its relationship to the Company (if the counterparty is a natural person and not a related party, the name may be omitted): To be announced after confirmation.

5. If the counterparty is a related party: reason for selection, previous owner, relationships among the previous owner, the Company and counterparty, previous transfer date and amount: Not applicable.

6. If the owner within the past five years was a related party of the Company, the date and price of acquisition/disposal and relationship at that time: Not applicable.

7. Estimated gain (or loss) on disposal (not applicable to asset acquisition; if deferred, list the recognition status): Not applicable.

8. Delivery or payment terms (including period and amount), contractual restrictions, and other important agreements:

Payment per contract terms.

9. Method of determining the transaction (bidding, price comparison, or negotiation), basis for price determination, and decision-making unit:

Determined through inquiry, comparison, and negotiation, approved by the competent authority.

決策單位:

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民國113年12月26日

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民國113年12月26日

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Automotive electrification still faces many technical challenges, and OEMs are focusing on overcoming them. To advance a sustainable future, engineers want to maximize EV range while cutting design complexity and external-component cost. Maximizing EV autonomy by reducing complexity and cost is a primary goal of the modern automotive vision. The EV ecosystem is profoundly shaped by silicon-carbide (SiC) power electronics, which deliver multiple performance advantages.

The automotive industry is undergoing a technology transformation. The transition from internal-combustion-engine (ICE) vehicles to EVs is spreading rapidly. At the same time, semiconductor innovations in traction-inverter systems and power conversion are helping overcome key barriers and enable wider adoption. Driven by global CO2-reduction regulations, EVs are expected to be widely adopted by 2030. Designers of high-voltage applications such as traction inverters now face the challenge of optimizing system efficiency and reliability within tight space constraints.

Today, automakers can produce reliable SiC- and IGBT-based traction inverters with advanced SiC monitoring, protection, and diagnostic functions to achieve functional safety. The latest generation of highly integrated SiC gate drivers maximizes EV autonomy. Achieving greater EV range also requires more efficient traction inverters. The characteristics of SiC gate drivers allow designers to raise power density, reduce design complexity and external-component count, lower cost, and meet strategic goals around functional safety and overall performance—maximizing autonomy and designing ever more efficient traction inverters.

安全無憂更新數百萬設備

Power-device technology specifications and target markets

SiC gate drivers help deliver more functionality with less power, making them ideal for many markets—especially today’s automotive sector—and offering advantages across a wide range of applications.

Efficient power conversion depends on the power semiconductors used in the system. As device technology improves, high-power applications are becoming more efficient and compact. Such devices include IGBTs and SiC MOSFETs, which combine high voltage and current ratings with low conduction and switching losses, making them ideal for high-power applications. Above 400V, devices must be rated above 650V to provide adequate safety margin. Industrial motor drives, EVs and hybrids, traction inverters, and solar inverters span power levels from a few kW to MW and beyond.

Power levels of SiC MOSFETs and IGBTs are very similar but diverge as frequency increases. SiC MOSFETs are increasingly common in PFC power supplies, solar inverters, EV/HEV traction inverters, motor drives, and rail traction. IGBTs remain more common in motor drives, UPS systems, string and central solar inverters below 3 kW, and EV/HEV traction inverters.

圖1：根據功率水準和頻率劃分的功率半導體元件應用示意圖。
(來源：德州儀器)

Compared with silicon MOSFETs and IGBTs, SiC MOSFETs offer several system-level advantages. Wide-bandgap (WBG) materials have very attractive properties; compared with silicon-based systems, SiC’s material characteristics translate directly into system-level benefits—smaller size, lower cost, and lighter weight. SiC MOSFETs are gradually replacing silicon power devices.

圖2：功率元件材料的技術特性。
(來源：德州儀器)

矽MOSFET、矽IGBT和SiC MOSFET都可用於電源應用，但在功率水準、驅動方法和工作模式上有所不同。功率IGBT和MOSFET在閘極採用電壓驅動，因為IGBT在內部是一個驅動雙極結型電晶體的MOSFET。由於IGBT具有雙極特性，因此它們能以較低的飽和電壓承載較大的電流，從而實現較低的傳導損耗。

MOSFET的傳導損耗也很低，但取決於元件的漏源導通電阻(RDS(on))。矽MOSFET承載的電流比IGBT小，因此IGBT用於大功率應用。MOSFET用於高頻應用，在這些應用中，高效率是最重要的。

SiC MOSFET在元件類型上與矽MOSFET相似。不過，SiC是一種WBG材料，其特性使這些元件能夠在與IGBT相同的大功率水準下工作，同時還能實現高頻率開關。這些特性轉化為重要的優勢，包括更高的功率密度、更高的效率和更低的散熱。隨著功率水準的增加，例如在驅動電動車馬達的牽引逆變器中，由於高極限工作溫度和容許結溫，IGBT等矽功率元件的散熱管理變得更加複雜。這就需要將冷卻元件整合到驅動系統中，尤其是在功率可能超過100kW的牽引逆變器中。然而，這些冷卻元件會增加車輛的尺寸、重量和成本。相比之下，SiC的容許結溫要高得多。此外，在給定電池容量的情況下，SiC斷路器在牽引逆變器系統中的效率比IGBT提高了10%。

SiC在車用電力電子系統中的重要性

SiC, a WBG semiconductor, has become a successful technology in recent years with the potential to reshape the sustainable transportation ecosystem globally. Using SiC for power switching improves EV powertrain power density and switching efficiency. Key advantages of SiC-based power electronics include:

．Higher power density, improving EV powertrain performance

．Operation at higher temperatures than conventional silicon devices

．Greater current-carrying capability

．Higher switching frequencies

．High blocking voltage

．Thermal conductivity 2–3× higher than silicon

．Longer driving range

．Faster charging

．Lower cost

SiC power devices offer up to five times the current density of silicon, enabling higher per-die power density, smaller devices, and more compact packages. As battery costs continue to drop with higher energy density, EV powertrains are also boosting power density by reducing size, weight, and cost—chiefly by maximizing use of SiC power switches, especially in on-board chargers (OBCs) and traction inverters.

In addition, SiC-based power devices can raise switching frequencies by 10×—at least 20 kHz in traction inverters and several hundred kHz in OBCs. At these higher frequencies, passive components such as capacitors and inductors can shrink significantly, enabling smaller overall systems. SiC enables higher voltage, higher power, and higher switching efficiency, simplifying high-power traction-inverter design and substantially reducing losses.

電動車系統工程師面臨的挑戰是，如何透過涉及電源轉換和WBG半導體的創新，最大限度地發揮高壓技術的潛力。電動車對更高可靠性和更高功率性能的需求不斷成長，因為效率的提高直接影響到每次充電續航里程的增加。然而，考慮到大多數牽引逆變器的效率已達到90%或更高，電動車設計人員要想大幅提高效率仍然非常困難。在電動車動力系統中使用SiC功率開關可實現更高的功率密度和開關效率。

此外，基於SiC的電力電子元件還能使電動車實現更長的行駛里程、更快的充電速度和更低的擁有總成本。還可利用SiC元件低功率損耗降低電池成本和尺寸。此外，更高的電壓可減少馬達繞組中對大量銅的需求，從而實現更小的馬達設計。這些元件尺寸和重量的減少有助於降低電動車的成本，從而大大有利於電動車的成本趨於平價，甚至優於傳統的內燃機汽車。在給定功率水準和電池容量的情況下，SiC功率元件的尺寸可以更小，從而形成具有整合推進系統的電動車子系統集群。在設計層面，透過消除或減少用於冷卻的機械塊，以及被動元件和外殼的材料用量，可以最大限度地降低系統成本。

總體而言，SiC電力電子技術正在產生巨大的全球影響。未來幾年SiC最大的細分市場肯定是電動車，這說明SiC技術市場的成長速度將超過電動車市場。

(參考原文：Why SiC Is at the Heart of E-Mobility，by Giordana Francesca Brescia)

本文同步刊登於《電子工程專輯》雜誌2024年6月號

Paragon noted that JingCheng Materials is a specialist supplier of SiC technology and materials. Though a young company, its team has worked in the compound-semiconductor industry for many years and is well versed in various semiconductor and single-crystal growth technologies as well as wafer processing.

SiC features high voltage and high-frequency capability, operates stably at high temperatures with lower power consumption, excellent heat dissipation, and a smaller footprint. With advantages in key parameters such as dielectric constant, thermal conductivity, and maximum operating temperature, it is well suited for power-semiconductor devices used in EVs, 5G communications, and solar energy—applications that must withstand extreme operating environments.

The SiC industry is closely tied to defense and aerospace. Export controls by leading nations have long produced a market oligopoly, making the technology hard to obtain. Although Taiwan is a semiconductor powerhouse, its SiC crystal development is still in its early stages. Meanwhile, the global SiC device market is growing at 60–70% annually with strong prospects, attracting Paragon to enter the field.

Paragon said the JingCheng acquisition lays the groundwork for future diversification and transformation, and hopes to enhance Taiwan’s international competitiveness in wide-bandgap power semiconductors, becoming a stable supply source of key materials amid global power competition.

In addition, Paragon swung to a loss last quarter on the impact of China’s lockdowns and notebook-industry inventory adjustments, with first-half EPS narrowing to NT$0.01. To navigate notebook market uncertainty, the company will tightly control costs; it recently announced the disposal of its plant operated by Zhejiang Junsheng Optoelectronics in the Sunshine Industrial Park, Dipu Town, Anji County, Huzhou City, to generate non-operating income and lower operating costs.